1. Field of the Invention
The present invention relates to sense amplifiers for use in memory devices, and more particularly to a latch type sense amplifier which has a negative feedback device to connect the bit lines to the output unit of the sense amplifier after the sense amplifier is enabled.
2. Discussion of Related Art
Generally, a sense amplifier is a circuit for detecting the voltage or current level of an input signal by a threshold voltage and then amplifying it and in some cases, it includes the function of detecting only the input signal of a predetermined time period.
This sense amplifier is generally used for a minute output signal of a memory device.
A typical type of sense amplifiers used in memory devices as described above is a latch type, and a current driving latch type sense amplifier is shown in FIG. 1.
FIG. 1 is a circuit diagram showing a latch type sense amplifier according to a prior art. The sense amplifier is comprised of third and fourth PMOS transistors MP3 and MP4 which have their source terminals connected a predetermined positive voltage VCC and are turned on/off by a precharge signal SEAQ applied to their gate terminals; a first PMOS transistor MP1 which has a source terminal connected to the positive voltage VCC and a drain terminal connected to the drain terminal of the fourth PMOS transistor MP4 and is turned on/off by the voltage of the drain terminal of the third PMOS transistor MP3 applied to its gate terminal; a second PMOS transistor MP2 which has a source terminal connected to the positive voltage VCC and a drain terminal connected to the drain terminal of the third PMOS transistor MP3 and is turned on/off by the voltage of the common drain terminal of the fourth and first PMOS transistors MP4 and MP1 applied to its gate terminal; a fourth NMOS transistor MN4 which has a drain terminal connected to the common drain terminal of the fourth and first PMOS transistors MP4 and MP1 and a gate terminal connected to the common drain terminal of the third and second PMOS transistors MP3 and MP2; a fifth NMOS transistor MN5 which has a drain terminal connected to the common drain terminal of the third and second PMOS transistors MP3 and MP2 and a gate terminal connected to the common drain terminal of the fourth and first PMOS transistors MP4 and MP1; a second NMOS transistor MN2 which has a drain terminal connected to the source terminal of the fourth NMOS transistor MN4 and a gate terminal connected to a first data line DATA; a third NMOS transistor MN3 which has a drain terminal connected to the source terminal of the fifth NMOS transistor MN5, a gate terminal connected to a second data line DATAB and a source terminal connected to the source terminal of the second NMOS transistor MN2; and a first NMOS transistor MN1 which has a drain terminal connected to the common source terminal of the second and third NMOS transistors MN2 and MN3 and a gate terminal connected to an enable signal SAC.
The operation of the above described current driving latch type sense amplifier is as follows.
The first NMOS transistor MN1 is turned on/off by the enable signal SAC, and if the first NMOS transistor MN1 is turned on, the sense amplifier starts operating. The second and third NMOS transistors MN2 and MN3 input data read-out from the memory cells (not shown) via the first and second data lines DATA and DATAB and then perform an initial operation of the sense amplifier. The fourth and fifth NMOS transistors MN4 and MN5 and the first and second PMOS transistors MP1 and MP2 constitute a latch unit, and the third and fourth PMOS transistors MP3 and MP4 are means which is turned on by the precharge signal SEAQ and initializes the potential of the output signals SOUT and SOUTB.
FIG. 2 shows a memory read circuit utilizing the prior art sense amplifier as described above. Referring to FIG. 2, the memory read circuit includes a memory cell 50 which stores data having opposite value to each other and outputs the stored data via the bit lines BIT and BITB according to the voltage state of the word line WL by the combination of the designated row addresses; a bit line precharge circuit 40 connected in parallel to the bit lines BIT and BITB connected to the memory cell 50, for precharging and equalizing the bit lines BIT and BITB by a control signal DTEQ; a column selecting circuit 30 controlled by a first column selection signal YSW and a second column selection signal YSWB having an opposite phase to the first column selecting signal YSW, for connecting the bit lines BIT and BITB to the data lines DATA and DATAB; a data line precharge circuit 20 connected in parallel to the data lines DATA and DATAB connected to the column selecting circuit 30, for precharging and equalizing the data lines DATA and DATAB by a control signal CDEQ; and a sense amplifier 10 for amplifying and outputting the data input via the data lines DATA and DATAB.
Only one memory cell 50 is shown in FIG. 2, however, a plurality of memory cells are actually connected in parallel to the bit lines BIT and BITB.
Hereinbelow, the operation of the memory read circuit as described above will be discussed.
If a word line WL is selected by a combination of the designated row addresses and a bit line is selected by a combination of the column addresses, that is, if the first column selection signal YSW is at a logic high state and the second column selection signal YSWB is at a logic low state, the data stored at the memory cell 50 are applied to an input unit of the sense amplifier 10 via the bit lines BIT, BITB and the data lines DATA, DATAB.
The bit line precharge circuit 40 is for precharging the voltage level of the bit lines BIT, BITB before the selected word line is enabled. That is, the PMOS transistors MP21 and MP22 serve to pull-up the bit lines BIT, BITB to a predetermined positive voltage VCC and the PMOS transistor MP25 serves to equalize the voltage difference between the bit lines BIT and BITB. In addition, the PMOS transistors MP23 and MP24 make the bit lines BIT and BITB maintain the positive voltage VCC at a normal state and prevent the greater voltage difference between the bit lines BIT and BITB at a read operation.
The data line precharge circuit 20 has the same function as the bit line precharge circuit 40, and the function of the PMOS transistors MP11 to MP13 constituting the data line precharge circuit 20 corresponds to that of the PMOS transistors MP25, MP21 and MP22 in the bit line precharge circuit 40.
The functions and problems of the sense amplifier used in the prior art memory read circuit will be discussed in detail with reference to FIG. 3.
Before the sense amplifier 10 is enabled, the data lines DATA and DATAB are precharged to the positive voltage VCC and the enable signal SAC and the precharge signal SEAQ are at the logic low levels, as shown in (C) of FIG. 3. Thereby, the first NMOS transistor MN1 is disabled, thus isolating the path for discharging the output node, and the third and fourth PMOS transistors MP3 and MP4 are turned on, thus raising the potentials of the both outputs to the positive voltage VCC level.
After the word line and column line are opened and the precharge operation for the bit lines and data lines is completed, i.e., if the control signals CDEQ and DTEQ input to the precharge circuits 20 and 30 for precharging the data lines and bit lines go to the logic high levels, as shown in (B) of FIG. 3, the voltage of the bit line connected to the low node of the memory cell 50 is lowered, thus generating the voltage difference between the bit lines BIT and BITB.
After delaying for a predetermined time, the enable signal SAC and the precharge signal SEAQ go to the logic high levels and thus the precharge operation for the sense amplifier 10 is completed and the sense amplifier starts sensing the input voltage difference (see (C) of FIG. 3). The minimum voltage difference dV1 (see (D) of FIG. 3) for preventing the malfunction of the sense amplifier 10 is identical to an offset voltage Vdffset generated by the asymmetrical element of the sense amplifier 10.
The second and third NMOS transistors MN2 and MN3 used as the input unit of the sense amplifier 10 convert the voltage difference between the data lines DATA and DATAB into the current difference. This converted current difference varies the discharging speed of the output unit, thereby generating the voltage difference between the both nodes of the output unit. The latch unit comprised of the fourth and fifth NMOS transistors MN4 and MN5 and the first and second PMOS transistors MP1 and MP2 decreases the voltage difference of the output unit, allowing a higher speed latching of the output unit.
If the voltage of the first data line DATA is higher than that of the second data line DATAB, the first output signal SOUT is latched to a logic high level and the second output signal SOUTB is latched to a logic low level. Once the output signals are latched, the first output signal SOUT maintains the logic high state by the second PMOS transistor MP2, thus turning off the fifth NMOS transistor MN5, and the second output signal SOUTB maintains the logic low state by the first, second and fourth NMOS transistors MN1, MN2 and MN4, thus turning off the first PMOS transistor MP1.
After the sense amplifier 10 is latched, the latched state is not changed even when the voltage difference between the data lines DATA and DATAB is changed. Thus, the latch type sense amplifier as described can achieve an operational stability.
On the contrary, if there occurs an asymmetry in the sense amplifier 10, the voltage difference as high as can compensate the offset voltage must be applied to the input unit, and this means that the sense amplifier must be enabled after there generates that much voltage difference between the bit lines after the word line is selected.
In order to reduce the time delay according thereto, the equalizing resistance of the PMOS transistors MP23 and MP24 having a DC pull-up function in the bit line precharge circuit 40 must be great.
However, as shown in FIG. 3, the voltage difference of the bit line pair is continuously increased even after the sense amplifier 10 is latched and then saturated at the value dV2 (see (D) of FIG. 3), and this value is determined according to the current driving power of the memory cell and the current driving power of the DC pull-up.
It is preferable to make the value dV2 small for a fast precharging of the bit lines when the read operation for another memory cell data starts by the address conversion. For this, the equalizing resistance of the DC pull-up must be small.
As described above, the prior art has a problem of conflicting requirements that the equalizing resistance of the DC pull-up must be great to reduce the time delay associated with the enable of the sense amplifier, while the equalizing resistance of the DC pull-up must be small for a fast precharge speed at an address conversion.